The present invention relates to a semiconductor memory device, and more particularly, to a data output control circuit that can control an internal operation to output data corresponding to an external command in synchronization with a system clock.
In a system with a variety of semiconductor devices, a semiconductor memory device serves as a data storage. The semiconductor memory device outputs data corresponding to addresses received from a data processor, e.g., a central processing unit (CPU), or stores data received from the data processor into unit cells selected by addresses input together with the data.
As the operating speed of the system increases, the data processor requires the semiconductor memory device to output and store data at higher speed. For the purpose of high-speed data input and output, a synchronous memory device was developed. The synchronous memory device inputs and outputs data in synchronization with a system clock. However, because even the synchronous memory device could not meet the required data input/output speed, a double data rate (DDR) memory device was developed. The DDR memory device inputs or outputs data at falling edges and rising edges of the system clock.
The DDR memory device must process two data during one cycle of the system clock so as to input/output data at a falling edge and a rising edge of the system clock. Specifically, the DDR memory device must output data exactly in synchronization with the rising edge and the falling edge of the system clock. To this end, a data output control circuit of the DDR memory device controls timings of outputting and transferring data to output the data in synchronization with rising and falling edges of the system clock.
The semiconductor memory device must output data corresponding to an external read command after several cycles of the system clock from the receipt of the external command. A column address strobe (CAS) latency (CL) represents a start timing of the data output. Generally, the semiconductor memory device supports multiple CLs and can adjust them according to operation environments. The CL is set in a mode register set (MRS). When the external read command is input, the semiconductor memory device determines a data output timing according to the CL set in the MRS.
However, the system clock inevitably has a delay time until it arrives at a data output circuit because it passes through a clock input buffer, a clock transmission line, etc. Thus, if the semiconductor memory device outputs data in synchronization with the delayed system clock, an external device will receive data that are not synchronized with rising edges and falling edges of the system clock. To solve this problem, the semiconductor memory device uses a delay locked loop (DLL) circuit to lock a delay of a clock signal. The DLL circuit compensates the delay caused by internal circuits of the semiconductor memory device until the system clock input to the semiconductor memory device is transferred to the data output control circuit.
In order to exactly output the data corresponding to the external command after the CL, the semiconductor memory device uses a data output control circuit that determines a data output timing by using a DLL clock output from a DLL circuit and a CL set in an MRS.
FIG. 1 is a block diagram of a data output control circuit in a typical semiconductor memory device.
Referring to FIG. 1, the data output control circuit includes a delay locked loop (DLL) circuit 110, an output signal generator 120, a clock divider 130, a synchronizer 140, a pre-driver 150 and a strobe generator 160. The data output control circuit receives an output enable signal and DLL clocks IRCLKDLL and IFCLKDLL to generate a data strobe signal DQS to indicate data output timing. The output enable signal is generated in response to a write command. The DLL clocks IRCLKDLL and IFCLKDLL are generated by compensating delay of an external clock CLK which is generated while the external clock are transferred in the semiconductor memory device.
Specifically, the DLL circuit 110 performs a delay locking operation on the external clock CLK using a clock pulse CLKP4 corresponding to rising edges of the external clock. As such, the DLL circuit 110 compensates internal delays of the external clock to output the DLL clocks IRCLKDLL and IFCLKDLL to the clock divider 130 and the output signal generator 120.
The output signal generator 120 generates a plurality of enable signals OE00, OE10, OE15, OE20, OE25, OE30, OE35 and OE40 in response to a read pulse CASP6_RD received from a command decoder (not shown). Durations of activation sections of the plurality of enable signals OE00, OE10, OE15, OE20, OE25, OE30, OE35 and OE40 are determined by a burst control signal YBSTA1 corresponding to a burst length (BL) set in an MRS. Then, the output signal generator 120 outputs rising and falling output enable signals ROUTEN and FOUTEN to the clock divider 130 by selecting one of the plurality of enable signals OE00, OE10, OE15, OE20, OE25, OE30, OE35 and OE40 according to a CL.
Also, the output signal generator 120 outputs a pre-enable signal QSENPRE to the synchronizer 140 to set operation margins of a data strobe signal DQS and control a data output buffer so that data D0, D1, D2 and D3 corresponding to the read command are output in synchronization with the data strobe signal DQS, before the output of the data strobe signal DQS. Here, the pre-enable signal QSENPRE is activated 0.5 tCK earlier than the rising output enable signal ROUTEN, and 1 tCK earlier than the falling output enable signal FOUTEN. In addition, the output signal generator 120 performs an OR operation on the pre-enable signal QSENPRE and the falling output enable signal FOUTEN to generate a strobe enable signal QSEN.
The clock divider 130 transfers the DLL clocks IRCLKDLL and IFCLKDLL and the rising and falling output enable signals ROUTEN and FOUTEN. The clock divider 130 serves as a driver for transferring the DLL clocks IRCLKDLL and IFCLKDLL and the rising and falling output enable signals ROUTEN and FOUTEN to each data pad of the semiconductor memory device.
The synchronizer 140 receives second DLL clocks RCLKDLL2 and FCLKDLL2, a second rising output enable signal ROUTEN2, and a second falling output enable signal FOUTEN2 from the clock divider 130, and receives the pre-enable signal QSENPRE from the output signal generator 120 to output a rising strobe signal RCLKDOQS, a falling strobe signal FCLKDOQS, a pre-operation signal QSPRECK, and an off signal QSOFF. The pre-operation signal QSPRECK and the off signal QSOFF are used to secure a pre-operation margin and a post-operation margin of the data strobe signal DQS. Specifically, the synchronizer 140 receives the second DLL clocks RCLKDLL2 and FCLKDLL2 from the clock divider 130 to output rising and falling strobe signals RCLKDOQS and FCLKDOQS when the second rising enable signal ROUTEN2 and a falling output enable signal FOUTEN2 are activated by the clock divider 130. In addition, the synchronizer 140 generates the pre-operation signal QSPRECK in synchronization with a rising edge of the pre-enable signal QSENPRE, and the off signal QSOFF in synchronization with a falling edge of the strobe enable signal QSEN.
Thereafter, the pre-driver 150 secures the pre-operation margin in response to the pre-operation signal QSPRECK, generates an internal strobe signal PRE_DQS in response to the rising and falling strobe signals RCLKDOQS and FCLKDOQS, and then secures the post-operation margin in response to the off signal QSOFF.
The strobe generator 160 receives the internal strobe signal PRE_DQS of a CMOS level from the pre-driver 150 to generate a data strobe signal DQS having a small voltage swing width according to a predefined specification.
FIG. 2 is a timing diagram illustrating an operation of the typical semiconductor memory device of FIG. 1.
Referring to FIG. 2, the DLL circuit 110 performs a delay locking operation on an external clock CLK to generate a rising DLL clock IRCLKDLL corresponding to a rising edge of the external clock CLK and a falling DLL clock IFCLKDLL corresponding to a falling edge of the external clock CLK.
When an external read command is input, the command decoder outputs a read pulse CASP6_RD. The read pulse CASP6_RD is input into the output signal generator 120 together with a burst control signal YBSTA1 corresponding to a BL set in the MRS. Also, the command decoder outputs an operation mode signal WT10BT11 corresponding to the read command. The operation mode signal WT10BT11 has a logic low level in a read mode, and a logic high level in a write mode. When command is applied, the operation mode signal WT10BT11 is input into the data output control circuit to indicate an operation to be performed by the semiconductor memory device.
The output signal generator 120 generates a plurality of enable signals OE00, OE10, OE15, OE20, OE25, OE30, OE35 and OE40 in response to the read pulse CASP6_RD. Activation timing of each enable signal is determined according to the rising and falling DLL clocks IRCLKDLL and IFCLKDLL, and a duration of the activation section is determined according to the burst control signal YBSTA1. The output signal generator 120 outputs rising and falling output enable signals ROUTEN and FOUTEN and a pre-enable signal QSENPRE by selecting respective enable signals among the plurality of enable signals OE00, OE10, OE15, OE20, OE25, OE30, OE35 and OE40 according to the CL set in the MRS. Also, the output signal generator 120 generates a strobe enable signal QSEN using the pre-enable signal QSENPRE and the falling output enable signal FOUTEN.
The synchronizer 140 extracts a rising strobe signal RCLKDOQS and a falling strobe signal FCLKDOQS using signals received from the clock divider 130, and generates a pre-operation signal QSPRECK and an off signal QSOFF of a clock type to secure a pre-operation margin and a post-operation margin of a data strobe signal DQS. Then, the pre-driver 150 generates an internal strobe signal PRE_DQS of a CMOS level, and the strobe generator 160 converts the level of the internal signal PRE_DQS to output a data strobe signal DQS.
Referring again to FIG. 2, when the BL is 4, data D0 to D3 are aligned with the data strobe signal DQS and output after CL from the receipt of the read command RD. In a general semiconductor memory device, data are input/output based on the external clock CLK. However, as the frequency of the external clock CLK increases and the data transferring speed increases, the phase of the external clock CLK can be affected by operation environments such as temperature, voltage level, and process. Therefore, in order to secure a stable data valid window for input/output data, a high-speed semiconductor memory device aligns data with a data strobe signal DQS before outputting them to the outside. Also, the data strobe signal DQS secures operation margins of logic low level before/after outputting the data D0 to D3 to prevent the data contention. In a high-speed semiconductor memory device, the data strobe signal DQS transits between a logic low level and a logic high level not to have a high voltage level difference. If the data strobe signal DQS transits to have a high voltage level difference like the external clock CLK, power consumption for operating the semiconductor memory device increases. If drivability of the strobe generator 160 is reduced to reduce the power consumption, the data strobe signal DQS cannot make up with the data input/output speed.
FIG. 3 is a timing diagram illustrating a problem of the typical semiconductor memory device of FIG. 1.
Referring to FIG. 3, in a high frequency operation, the data strobe signal DQS has a logic low level of a ground voltage level for a predetermined pre-operation margin. At a time point of outputting the first data (i.e., after CL from the input of the read command), a first logic level transition occurs. Here, the data strobe signal DQS transits from a ground voltage level (0 V) to a logic high level. However, swing widths of the following transitions are reduced to reduce power consumption and ensure a high-speed performance.
Since the drivability of the strobe signal DQS is adjusted to output a data strobe signal DQS of a reduced swing width, the transition of the data strobe signal DQS at the point of outputting the first data is delayed to some degree. This means that the data valid window of the first output data becomes smaller than those of other following data.